The present invention concerns complex integrated circuits, and more particularly microprocessors, that are circuits capable of carrying out not only a single, well-defined function, but also a variety of different functions. Instructions, received at the input of the microprocessor in the form of coded signals, determine the functions to be carried out. The succession of the instructions received determines the sequence of a complex numerical processing performed by the microprocessor on data also received at the input of the microprocessor.
The microprocessors are circuits of which the complexity is such that their conception requires years of work for the teams that are responsible for this conception.
Not only it is long and difficult to conceive schemas of electric circuits allowing to carry out all the functions desired but furthermore it is necessary to provide that these schemas can be integrated on a silicon chip having reasonably small dimensions, i.e. compatible with sufficient manufacturing yields.
From this necessity results a very large topological implantation or xe2x80x9clay-outxe2x80x9d, allowing to place in position the different circuit elements within a surface as small as possible. Often, this lay-out work leads to restructuring the electric schemas themselves so that the conception work of the circuit itself and the lay-out work become closely linked.
Furthermore, a microprocessor comprises circuits of which the electrical functions are overall the same for the different microprocessors; accumulators, various registers, instruction decoders, digital and logic unity; possible read-only memories (ROM) and random-access memories (RAM) when they are integrated on the same chip as the microprocessor per se.
When a conception team has worked over a long period on a microprocessor, it wishes to be able to reuse in their definite form, without modifying them or only slightly modifying them, certain parts of the microprocessor which would well be adapted to another microprocessor of the same type. The reutilization allows considerable savings on conception costs, increasingly so since parts whose working has been checked on effectively manufactured microprocessors will be reused; the reutilization without notable modification guarantees correct functioning without requiring new tests for the important units of the new microprocessor.
In order to allow more simply such reutilization of circuit parts having already proved their aptitude at correct functioning, it is desirable to provide that the general structure of the circuit can be adapted to this reutilization; it must be adapted both with respect to the electrical functionality and with respect to the lay-out: it two different clearly distinct functions are toplogically imbricated within each other, it will be practically impossible to decide to profitably reutilize one of the functions without the other. Furthermore, the fact that the groups of circuit elements appear to form topologically units clearly distinct from one another is not a reason for considering that these units can be profitably reutilized if the separation of the functions is not as definite as the topological separation of the units.
The invention concerns more particularly the part of the microprocessor that is called the xe2x80x9cinstruction sequencerxe2x80x9d and of which the function is the following: it receives binary signals representing the instructions to be carried out, signals which are present in the form of several bits in parallel stored in an instruction register; upon a determined instruction, corresponding to a group of well defined bits, the sequencer causes to correspond one or several control signals appearing respectively on the output control lines of the sequencer. These control lines are connected to logic gates or registers or other circuit elements; an instruction actuates a certain number of control lines, in such a manner as to open the logic gates (for example) or load the registers, etc. . . while another instruction will open other gates or will load other registers.
Taking into account the complexity of the functions carried out by the microprocessor, each instruction generally activates several control lines and reciprocally a single control line can be activated by several instructions.
This means that the binary signal which appears on each control line must be a boolean function (sum of products) of the bits constituting the instructions.
The sequencer thus essentially comprises a decoder comprising multiplying AND gates giving the products followed by adding OR gates giving the sums. In a classical manner, it is furthermore possible without any drawback to replace these gates by NOR gates in cascade with other NOR gates.
Thus for decoding, a transistor matrix or network in lines and columns is first of all generally used for carrying out the NOR functions on the instructions bits; the bits and their complements arrive on the columns and each line establishes a NOR function of a particular association of the bits and of their complements; the programming of this NOR function is determined by the presence or absence of a transistor at the intersection of the line with the different columns.
It is well understood that this first decoding is insufficient since it only achieves associating a NOR gate output to a determined instruction. It is thus necessary to complete this decoding in order to associate between one another several outputs of this network in such a manner that certain control lines are common to several different instructions while reciprocally certain instructions each activate several control lines.
The known sequences widely use this first transistor matrix for carrying out the first part of the instructions decoding; the use of such a matrix is in fact advantageous with respect to space required and manufacturing facility.
But with respect to the rest of the decoding, the known sequencers use solutions that are not at all optimal from the point of view of space required, ease of manufacturing, and facility of reutilization in other microprocessors; one solution uses another complete network of transistors but then on the one hand this network is very space consuming, and on the other hand, the outputs of the second network are perpendicular to the outputs of the first network; another solution uses NOR, NAND, and other logic gates that carry out the boolean functions required but which are topologically disposed in a totally random manner; this solution uses a minimum of elements but consumes a great amount of space for the passage of the electrical connections to and from these gates. Furthermore, they are not adaptable to a modular structure where the logic units are placed side by side, one unit being able to be replaced by a slightly different unit if the conception of the microprocessor is modified.
The present invention proposes a sequencer structure that is distinguished from known sequencers by its architecture, its electrical schema and its lay-out, these three combined components allowing to achieve a sequencer which on the one hand occupies a particularly reduced semiconductive surface and which on the other hand is constituted by juxtapositioned units facilitating reutilization of certain parts during the conception of another microprocessor having similar characteristics.
The instructions sequencer for microprocessor according to the invention has the following constitution:
(a) its inputs are connected to input conductors extending along the length of the first parallel columns;
(b) each first column comprises a plurality of decoding transistors that are furthermore disposed in lines, a transistor placed at the intersection of a line and a column having its grid connected to the input conductor and its drain connected to a line conductor taken among a group of first line conductors that each correspond to a respective line;
(c) each first line conductor is connected to a first preload transistor corresponding to this line, transistor of which the grid is controlled by a first clock signal, the first preload transistors being placed along the length of a second column parallel to the first columns;
(d) each first line conductor is also connected to a first capacitor corresponding to this line, the first capacitors being placed along the length of a third column parallel to the first columns;
(e) each first line conductor is also connected to the source of a first sampling transistor corresponding to this line, transistor of which the grid is controlled by a second clock signal and of which the drain is connected to a line conductor taken from among a group of second line conductors corresponding each to a respective line, the first sampling transistors being placed along the length of a fourth column parallel to the others;
(f) the drain of each first sampling transistor is also connected to a second respective capacitor and the second capacitors are placed along the length of a fifth column parallel to the others;
(g) each second line conductor is connected to the grid of a transistor placed along the length of a sixth column, the drain of this transistor being connected to the input of a controlled gate, and the transistor sources of the sixth column all being connected at the same point;
(h) the controlled gates are placed along the length of a seventh column parallel to the others and they each have an output connected on the one hand to a third respective capacitor, on the other hand a respective second preload transistor and finally to the source of a second sampling transistor, the three capacitors being placed along the length of an eighth column parallel to the others, the second preload transistors being placed along the length of a ninth column parallel to the others and having their grid controlled by a third clock signal, the second sampling transistors being placed along the length of a tenth column and having their grid controlled by a fourth clock signal.